1. Field of the Invention
The present invention relates generally to a mobile communication system, and in particular, to an apparatus and method for coding/decoding block low density parity check (LDPC) codes.
2. Description of the Related Art
With the introduction of a cellular mobile communication system in the U.S. in the late 1970's, South Korea started to provide a voice communication service in an Advanced Mobile Phone Service (AMPS) system, a first generation (1G) analog mobile communication system. In the mid 1990's, South Korea commercialized a Code Division Multiple Access (CDMA) system, a second generation (2G) mobile communication system, to provide voice and low-speed data services.
In the late 1990's, South Korea partially deployed an IMT-2000 (International Mobile Telecommunication-2000) system, a third generation (3G) mobile communication system, aimed at advanced wireless multimedia services, worldwide roaming, and high-speed data services. The 3G mobile communication system was especially developed to transmit data at a high rate in compliance with the rapid increase in the amount of serviced data. That is, the 3G mobile communication system has evolved into a packet service communication system, and the packet service communication system transmits burst packet data to a plurality of mobile stations and is designed for the transmission of mass data. The packet service communication system is being developed for a high-speed packet service.
The 3G mobile communication system is evolving into a fourth generation (4G) mobile communication system. The 4G mobile communication system is under standardization for standardizing the interworking and integration between a wired communication network and a wireless communication network beyond simple wireless communication service that the previous-generation mobile communication systems provided. Technology for transmitting large volumes of data at and up to a capacity level available in the wired communication network must be developed for the wireless communication network.
As a high-speed, high-capacity communication system capable of processing and transmitting data such as image and radio data as well as simple voice service data is required, it is necessary to increase the system transmission efficiency using an appropriate channel coding scheme in order to improve the system performance. A mobile communication system inevitably experiences errors occurring due to noise, interference and fading according to a channel condition during data transmission. The occurrence of the errors causes a loss of information data.
In order to reduce the information data loss due to the occurrence of errors, it is possible to improve reliability of the mobile communication system by using various error-control techniques. One technique using an error-correcting code is the most popularly used error-control technique. A description will now be made of a turbo code and a low density parity check (LDPC) code, which are typical error correcting codes.
Turbo Code
The turbo code is an error correcting code used in both a synchronous 3G mobile communication system and an asynchronous 3G mobile communication system. It is well known that the turbo code is superior in performance gain to a convolutional code previously used as a main forward error correction code, during high-speed data transmission. In addition, the turbo code is advantageous in that it can efficiently correct an error caused by noises generated in a transmission channel, thereby increasing the reliability of the data transmission.
LDPC Code
The LDPC code can be decoded using an iterative decoding algorithm base on a sum-product algorithm of a factor graph. Because a decoder for the LDPC code uses the sum-product algorithm-based iterative decoding algorithm, it is less complex than a decoder for the turbo code. In addition, the decoder for the LDPC code is easy to implement with a parallel processing decoder, compared with the decoder for the turbo code. When the LDPC code is expressed with a factor graph, cycles exist on the factor graph of the LDPC code. It is well known that iterative decoding on the factor graph of the LDPC code where cycles exist is less than optimized (sub-optimal). Also, it has been experimentally proved that the LDPC code has excellent performance through iterative decoding. However, when many cycles with a short length exist on the factor graph of the LDPC code, the LDPC code suffers from performance degradation. Therefore, studies are continuously being conducted to develop a technique for designing a LDPC code such that no cycles with short lengths exist on the factor graph of the LDPC code.
A coding process of the LDPC code has evolved into a coding process that uses a parity check matrix having a low weight density due to a characteristic of a generating matrix generally having a high weight density. The “weight” represents an element having a non-zero value from among the elements constituting the generating matrix and parity check matrix. In particular, if a partial matrix corresponding to a parity in the parity check matrix has a regular format, more efficient coding is possible.
Because the LDPC code includes various codes having a non-zero value, it is very important to develop an efficient coding algorithm and an efficient decoding algorithm for various types of LDPC codes in putting the LDPC code to practical use. In addition, because the parity check matrix of the LDPC code determines the performance of the LDPC code, it is also very important to design a parity check matrix having excellent performance. That is, an efficient parity check matrix having excellent performance, an efficient coding algorithm, and an efficient decoding algorithm must be simultaneously considered in order to generate a high-performance LDPC code.
One LDPC code is defined by a parity check matrix in which major elements have a value of 0 and minor elements except the elements having the value of 0 have a value of 1. For example, an (N, j, k) LDPC code is a linear block code having a block length N, and is defined by a sparse parity check matrix in which each column has j elements having a value of 1, each row has k elements having a value of 1, and all of the elements except for the elements having the value of 1 all have a value of 0.
An LDPC code in which a weight value of each column in the parity check matrix is fixed to T and a weight value of each row in the parity check matrix is fixed to ‘k’ as stated above, is called a “regular LDPC code.” Herein, the weight value represents the number of weights. Unlike the regular LDPC code, an LDPC code in which the weight value of each column in the parity check matrix and the weight value of each row in the parity check matrix are not fixed is called an “irregular LDPC code.” It is generally known that the irregular LDPC code is superior in performance to the regular LDPC code. However, in the case of the irregular LDPC code, because the weight value of each column and the weight value of each row in a parity check matrix are not fixed, i.e. are irregular, the weight value of each column in the parity check matrix and the weight value of each row in the parity check matrix must be properly adjusted in order to guarantee the excellent performance.
With reference to FIG. 1, a description will now be made of a parity check matrix of an (8, 2, 4) LDPC code as an example of an (N, j, k) LDPC code.
FIG. 1 is a diagram illustrating a parity check matrix of a general (8, 2, 4) LDPC code. Referring to FIG. 1, a parity check matrix H of the (8, 2, 4) LDPC code is comprised of 8 columns and 4 rows, wherein a weight value of each column is fixed to 2 and a weight value of each row is fixed to 4. Because the weight value of each column and the weight value of each row in the parity check matrix are regular as stated above, the (8, 2, 4) LDPC code illustrated in FIG. 1 becomes a regular LDPC code.
A factor graph of the (8, 2, 4) LDPC code described in connection with FIG. 1 will be described herein below with reference to FIG. 2.
FIG. 2 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG. 1. Referring to FIG. 2, a factor graph of the (8, 2, 4) LDPC code is comprised of 8 variable nodes of x1 211, x2 213, x3 215, x4 217, x5 219, x6221, x7 223 and x8 225, and 4 check nodes 227, 229, 231 and 233. When an element having a weight, i.e., a value of 1, exists at a point where an ith row and a jth column of the parity check matrix of the (8, 2, 4) LDPC code cross each other, a branch is formed between a variable node xj and a ith check node.
Because the parity check matrix of the LDPC code has a small weight value as described above, it is possible to perform the decoding through a iterative decoding process even in a block code having a relatively long length, that exhibits a performance approximating a capacity limit of a Shannon channel such as a turbo code while continuously increasing a block length of the block code. It has been proven that an iterative decoding process of an LDPC code using a flow transfer technique is almost approximate to an iterative decoding process of a turbo code in performance.
In order to generate a high-performance LDPC code, the following conditions should be satisfied.
(1) Cycles on a Factor Graph of an LDPC Code should be Considered.
The “cycle” refers to a loop formed by the edges connecting the variable nodes to the check nodes in a factor graph of an LDPC code, and a length of the cycle is defined as the number of edges constituting the loop. A cycle being long in length means that the number of edges connecting the variable nodes to the check nodes constituting the loop in the factor graph of the LDPC code is large. In contrast, a cycle being short in length means that the number of edges connecting the variable nodes to the check nodes constituting the loop in the factor graph of the LDPC code is small.
As cycles in the factor graph of the LDPC code become longer, the performance efficiency of the LDPC code increases, for the following reasons. That is, when long cycles are generated in the factor graph of the LDPC code, it is possible to prevent the performance degradation such as an error floor occurring when too many cycles with a short length exist on the factor graph of the LDPC code.
(2) Efficient Encoding of an LDPC Code should be Considered.
It is hard to subject the LDPC code to real-time coding compared with a convolutional code or a turbo code because of its high coding complexity. In order to reduce the encoding complexity of the LDPC code, a Repeat Accumulate (RA) code has been proposed. The RA code also has a limitation in the reduction the encoding complexity of the LDPC code. Therefore, an efficient encoding of the LDPC code should be considered.
(3) Degree Distribution on a Factor Graph of an LDPC Code should be Considered.
Generally, an irregular LDPC code is superior in performance to a regular LDPC code, because a factor graph of the irregular LDPC code has various degrees. The “degree” refers to the number of edges connected to the variable nodes and the check nodes in the factor graph of the LDPC code. Further, “degree distribution” on a factor graph of an LDPC code refers to a ratio of the number of nodes having a particular degree to the total number of nodes. It has been proved that an LDPC code having a particular degree distribution is superior in performance.
FIG. 3 is a diagram illustrating a parity check matrix of a general block LDPC code. Before a description of FIG. 3 is given, it should be noted that the block LDPC code is a new LDPC code for which not only efficient coding but also efficient storage and performance improvement of a parity check matrix were considered, and the block LDPC code is an LDPC code extended by generalizing a structure of a regular LDPC code. Referring to FIG. 3, a parity check matrix of the block LDPC code is divided into a plurality of partial blocks, and a permutation matrix is mapped to each of the partial blocks. In FIG. 3, ‘P’ represents a permutation matrix having an Ns×Ns size, and a superscript (or exponent) aij of the permutation matrix P is either 0≦aij≦Ns−1 or aij=∞. In FIG. 3, p represents the number of the row of the partial blocks, and q represents the number of the column of the partial blocks. The ‘i’ means that a corresponding permutation matrix is located in the ith row of the partial blocks of the parity check matrix, and the T means that a corresponding permutation matrix is located in the jth column of the partial blocks of the parity check matrix. That is, Paij is a permutation matrix located in a partial block crossed with the ith row and the jth column.
The permutation matrix will now be described with reference to FIG. 4.
FIG. 4 is a diagram illustrating the permutation matrix P of FIG. 3. As illustrated in FIG. 4, the permutation matrix P is a square matrix having an Ns×Ns size, and each of Ns columns constituting the permutation matrix P has a weight of 1 and each of Ns rows constituting the permutation matrix P also has a weight of 1.
In FIG. 3, a permutation matrix with a superscript aij=0, i.e. a permutation matrix P0, represents an identity matrix INs×Ns, and a permutation matrix with a superscript aij=∞, i.e. a permutation matrix P∞, represents a zero matrix.
In the entire parity check matrix of the block LDPC code illustrated in FIG. 3, because the total number of rows is Ns×p and the total number of columns is Ns×q (for p≦q), when the entire parity check matrix of the LDPC code has a full rank, a coding rate can be expressed as Equation (1) regardless of a size of the partial blocks.
                    R        =                ⁢                                                                              N                  s                                ×                q                            -                                                N                  s                                ×                p                                                                    N                s                            ×              q                                =                                                    q                -                p                            p                        =                          1              -                              p                q                                                                        (        1        )            
If aij≠∞ for all i and j, the permutation matrixes corresponding to the partial blocks are not zero matrixes, and the partial blocks constitute a regular LDPC code in which the weight value of each column and the weight value of each row in each of the permutation matrixes corresponding to the partial blocks are p and q, respectively. Here, each of permutation matrixes corresponding to the partial blocks will be referred to as “partial matrix.”
Because (p−1) dependent rows exist in the entire parity check matrix, a coding rate is higher than the coding rate calculated by Equation (1). In the case of the block LDPC code, if a weight position of a first row of each of the partial matrixes constituting the entire parity check matrix is determined, the weight positions of the remaining (Ns−1) rows are determined. Therefore, the required size of a memory is reduced to 1/Ns as compared with the case where the weights are irregularly selected to store information on the entire parity check matrix.
FIG. 5 is a diagram illustrating a parity check matrix of a general regular block LDPC code. The parity check matrix illustrated in FIG. 5 is a parity check matrix of an (s,r) array code, i.e. a regular block LDPC code. The (s,r) array code proposed is a typical regular block LDPC code, and the (s,r) array code corresponds to a block LDPC code for Ns=s and q=s and p=r in FIG. 3. Here, ‘s’ is an odd prime number, and ‘r’ always satisfies the condition r≦s.
A parity check matrix of the (s,r) array code has s2 columns and r×s rows, and a rank thereof becomes r×(s−1). The reason the rank of the parity check matrix of the (s,r) array code becomes r×(s−1) is because in the case where r partial matrixes in a row direction of the parity check matrix of the (s,r) array code, if s rows in each of the partial matrixes are summed up, a matrix in which all of the elements have a value of 1 is generated. That is, because r rows in which all elements have a value of 1 are generated, it can be understood that there are r dependent rows. Therefore, a coding rate Rarray of the (s,r) array code can be expressed as Equation (2)
                              R          array                =                ⁢                                                            s                2                            -                              r                ×                                  (                                      s                    -                    1                                    )                                                                    s              2                                =                                    1              -                                                r                  ×                                      (                                          s                      -                      1                                        )                                                                    s                  2                                                      >                          1              -                              r                s                                                                        (        2        )            
As described above, it can be noted that in the case of the (s,r) array code, a cycle with a length 4 does not exist in a factor graph because of an algebraic characteristic thereof, and can also reduce a memory capacity as stated above.
However, because the (s,r) array code is a regular LDPC code, it is inferior to an irregular LDPC code in performance degradation. Further, the block LDPC code cannot guarantee excellent performance, because the randomness thereof is low. That is, the (s,r) array code, although efficient coding was considered, still has a high coding complexity, and in the (s,r) array code, although a cycle with a length of 4 exists, a cycle with a length of 6 also exists. Further, because a degree distribution is not considered, performance degradation occurs.
FIG. 6 is a diagram illustrating a parity check matrix of a general irregular block LDPC code. Before a description of FIG. 6 is given, it should be noted that an irregular block LDPC code is a block LDPC code given by modifying the array code described in conjunction with FIG. 5 while taking into consideration the efficient coding. In the parity check matrix of the irregular block LDPC code illustrated in FIG. 6, ‘k’ and ‘r’ are integers satisfying the condition k,r≦s (for s=prime number), T denotes an identity matrix with a s×s size, and ‘0’ denotes a zero matrix with a s×s size. The parity check matrix of the irregular block LDPC code illustrated in FIG. 6 corresponds to a parity check matrix of a block LDPC code for Ns=s, q=k and p=r in FIG. 3.
For the efficient coding of the LDPC code, coding was enabled within a linear time by forming a partial matrix corresponding to a parity in the entire parity check matrix as a full lower triangular matrix as illustrated in FIG. 6. A structure of the entire parity check matrix, i.e. a structure of a partial matrix corresponding to an information word and a partial matrix corresponding to a parity, will be described herein below. When the partial matrix corresponding to a parity is formed as a full lower triangular matrix in this way, the parity check matrix always has a full rank because of a structural characteristic thereof. Therefore, a block length of a modified array code, i.e. an irregular LDPC code, becomes ks, and a coding rate R can be expressed as Equation (3)
                    R        =                ⁢                                            k              -              γ                        k                    =                      1            -                          γ              k                                                          (        3        )            
However, the irregular LDPC code of FIG. 6, having a parity check matrix in which a partial matrix corresponding to a parity has the form of a full lower triangular matrix, is more efficient than the array code, but the degree of distribution on a factor graph, which must be considered during the generation of an LDPC code, was not considered, and the removal of cycles with a short length was also not considered. Therefore, it is lower than the irregular LDPC code having a randomness in an error correcting capability. Accordingly, there is a demand for an irregular LDPC code that maximizes error correcting capability.